Summary
What you’ll impact
The Senior Compiler Engineer designs and implements compiler features that maximize hardware efficiency for an energy‑optimized programmable processor. This role leverages C++ and compiler frameworks such as LLVM, GCC, or MLIR to target a custom data‑flow ISA, handling memory ordering and power‑aware optimizations. Key duties include writing unit and integration tests, debugging functional and performance issues, and translating machine‑learning models from frameworks into optimized code for the hardware. The engineer collaborates with hardware architects and application developers to refine the architecture, provide debugging tools, and ensure integration of TinyML applications.
Responsibilities
What you'll do
- Develop new compiler features to improve overall hardware efficiency while maintaining programmability. These may relate to:
- Efficient’s new dataflow ISA
- Memory analysis and ordering Hardware constraints such as timing and power consumption
- Place-and-route of applications onto Efficient’s fabric
- Visualization
- Programmer debugging tools
- Write unit and integration tests to uncover functional- and performance-related compiler bugs.
- Work with various machine-learning frameworks to compile models to our custom hardware.
- Debug and fix functional and performance issues of the compiler system.
- Collaborate with the hardware and physical design team to understand and improve hardware architecture and propose future improvements.
- Work closely with the application development team to understand the problem domain and deliver optimized compiler solutions.
Requirements
What you’ll bring
- 6+ years of experience with C++.
- Bachelor's/Master's degree in CS or related field.
- Familiarity with compiler frameworks such as GCC, LLVM, and/or MLIR.
- Understanding of computer architecture and optimization.
- Experience using industry standard development and debugging tools including GDB.
- Strong attention to detail, good work ethic, ability to work on multiple projects simultaneously, and good communication skills.
- Good problem solving skills.
- Familiarity with FPGA-compilation and/or PnR algorithms.
- Experience with verilog, system verilog, or VHDL.
- Knowledge of computer architecture.